Suggestions
Aseem Gupta
Seeking ASIC Physical Design Opportunities
Professional Background
Aseem Gupta is a highly skilled engineer specializing in digital integrated circuit (IC) design, with a comprehensive background in ASIC physical design. He has extensive experience in the RTL-to-GDSII design flow using industry-standard Cadence EDA tools, which positions him as an expert in the field of digital implementation. Aseem's career has also expanded into the realm of analog and mixed-signal design, where he adeptly integrates digital modules into mixed-signal environments. His work with Cadence Virtuoso OA and EDI interoperability demonstrates his proficiency in drawing analog layouts for custom cells, particularly for deep sub-micron technologies.
Aseem's tool proficiency spans both front-end and back-end methodologies, including IUS, RTL Compiler, Simvision, Synopsys Design Compiler, SoC Encounter EDI, Cadence Virtuoso, Assura, Calibre, and PVS. This diverse skill set empowers him to address various challenges within the ASIC design landscape effectively.
A notable highlight of Aseem's career is his contribution to the field of high-energy physics. He successfully designed a mixed-signal fully custom ASIC to be used in the Phase 1 upgrade of the ATLAS and sTGC detectors for the Large Hadron Collider experiment at CERN in Geneva. This project exemplifies his ability to work on complex, large-scale projects that require precision and innovation.
Currently, Aseem is actively seeking a full-time position in ASIC/Digital/Mixed-Signal Design that allows him to leverage his skills and experience towards the development of efficient ASIC/SoC design tape-outs, with an emphasis on reducing design cycle time. His passion for the field and commitment to excellence make him a valuable asset for any organization in need of his expertise.
Education and Achievements
Aseem Gupta pursued his academic endeavors with diligence, culminating in a Master’s degree in Electrical and Computer Engineering from Stony Brook University. His foundational knowledge in engineering was solidified with a Bachelor's degree in Instrumentation and Control Engineering from Netaji Subhas Institute of Technology, where he developed a strong understanding of the principles that govern modern engineering practices.
Throughout his academic journey, Aseem served as a Teaching Assistant for Advanced VLSI Design at Stony Brook University, showcasing his commitment to education and his capability to impart knowledge to aspiring engineers. He also attended the Stanford Graduate School of Business's Design Thinking program, where he gained insights into transforming innovations into viable business solutions.
Achievements
Aseem’s career is a testament to his dedication to the field of integrated circuit design, marked by significant achievements and contributions to high-profile projects. His design for the ATLAS and sTGC detectors at CERN is particularly noteworthy, not only for its technical complexity but also for its impact on scientific research and experimentation at one of the world’s largest and most respected laboratories.
By consistently seeking opportunities for professional growth and applying his knowledge in practical settings, Aseem is poised to make continued strides in the field of ASIC and digital design. His proactive approach and extensive background ensure that he will excel in future endeavors and contribute meaningfully to his next organization.